NXP Semiconductors /MIMXRT1052 /ENC1 /TST

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Interpret as TST

TEN=TEN_0, TCE=TCE_0, QDN=QDN_0

Test Register

TEST_COUNT	These bits hold the number of quadrature advances to generate.
TEST_PERIOD	These bits hold the period of quadrature phase in IPBus clock cycles.
QDN	Quadrature Decoder Negative Signal 0 (QDN_0): Leaves quadrature decoder signal in a positive direction 1 (QDN_1): Generates a negative quadrature decoder signal
TCE	Test Counter Enable 0 (TCE_0): Test count is not enabled 1 (TCE_1): Test count is enabled
TEN	Test Mode Enable 0 (TEN_0): Test module is not enabled 1 (TEN_1): Test module is enabled

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